STUART F. OBERMAN

stuart@oberman.net

www.oberman.net


EDUCATION

 

EMPLOYMENT

October 2002 Present

Principal Engineer, NVIDIA, Santa Clara, CA.

September 1999 October 2002

Manager, VLSI Design, Nishan Systems, San Jose, CA.
Architect and Team Leader of 64G switch fabric chipset; Led team of 5 engineers in design and verification of switch fabric; Wrote architectural specification for 32G and 64G versions of the chipset; Coded several RTL modules; Participated in chipset verification; Implemented physical design of both chipsets in Virtex-II FPGAs, including all logic synthesis, floorplanning, I/O selection and placement, and individual module placement and routing; Successfully validated 32G chipset in multiprotocol storage switch platform, including signal integrity analysis and full chip-level and system-level diagnostics.

Architect and Team Leader of Traffic Managers for high density storage / LAN switch; Led team of 10 engineers in design and verification of traffic manager ASICs and FPGAs; Co-wrote architectural specification for entire chassis switch; Wrote micro-architectural specification for 10G Traffic Manager ASIC; Wrote micro-architectural specification for 4G Traffic Manager FPGA; Designed new algorithms for packet scheduling, congestion avoidance, and buffer management; Coded several RTL modules for 4G Traffic Manager; Led physical design of 4G Traffic Manager; Evaluated many 3rd party high density switch fabric chipsets supporting 10G and 40G line cards; Evaluated many 3rd party 10G and 40G network processors chips

- Lead designer of switch engine ASIC for medium density storage / LAN switch; Wrote micro-architectural specification; Coded several RTL modules; Participated in physical design; Led verification team

October 1999 April 2000

Architecture Consultant, SiByte / Broadcom, Santa Clara, CA.
Consulted on the design and implementation of a system-on-a-chip targeted to set-top boxes and networking applications.

November 1995 - September 1999

Senior Member of the Technical Staff, AMD, Sunnyvale, CA.
- Architect of multimedia unit; developed 2D, 3D, and video algorithms and hardware for integration into next-generation microprocessor
- Architect of the Athlon/K7 floating point unit; performed algorithm, RTL and logic design for the Athlon FPU
- Architect of the AMD 3DNow! instruction set; co-developed set of single-precision vector FP instructions to enhance 3D graphics and audio; performed algorithm, RTL, and logic design for the K6-2 implementation of these instructions
- Logic designer; improved the algorithms, logic and circuits of the K6 FPU

November 1996 August 2000

Consulting Assistant Professor, Electrical Engineering Department, Stanford University
Performed research in algorithms and implementations for high-performance floating-point arithmetic and computer architecture in the
Stanford Architecture and Arithmetic Group.

September 1992 - December 1996

Research Assistant, Electrical Engineering Department, Stanford University
Performed research in algorithms and implementations for high-performance computer architecture and floating-point arithmetic in the
Stanford Architecture and Arithmetic Group under the direction of Professor Michael J. Flynn.

November 1995 - January 1996

Floating-Point Consultant, Toshiba America, San Jose, CA.
Consulted on the design and implementation of a next-generation high performance floating-point unit.

April - July 1995

Logic Design Consultant, Integrated Information Technology (8x8, Inc), Santa Clara, CA.
Performed logic design, control logic synthesis, and critical path design for a high-performance microprocessor.

April - October 1994

Floating-Point Consultant, Vertex Semiconductor, San Jose, CA.
Performed logic design, control logic synthesis, and critical path design for a high-performance floating-point adder and multiplier.

Summer 1993

Research Intern, DEC Western Research Laboratory, Palo Alto, CA
Designed and implemented a time and event-driven inline simulator for a low power, low cost Alpha processor. Analyzed system performance and power for various datapath and memory system configurations.

ENGINEERING SERVICE

PATENTS

+ Several patents filed in the areas of packet scheduling, traffic management, and switch fabrics for storage and IP switches

 

PUBLICATIONS

Book

Journals

Conferences

Technical Reports